Description #

Updated version of the OrangeCrab, an electronics development board featuring a Lattice ECP5 FPGA, and DDR3 memory. Primarily designed to prototype RISCV SoC and evaluate custom peripherals.

This updated version improved the multiboot experience by connecting an FPGA I/O to the reset line.

This version was produced as a small batch for a GroupGets campaign.

Technical details #

Here are the main details for the OrangeCrab (25F)

• Lattice ECP5-25F FPGA in csfBGA285 package
  • 24 K - Look Up Tables
  • 1008 Kb - Embedded Block RAM
  • 194 Kb - Distributed RAM
  • 28 - 18x18 Multipliers
  • PLLs: 2
  • Internal oscillator
  • Flexible I/O for DDR3 Memory Support
• DDR3L Memory
  • 128 Mbytes (1Gbit)
  • 64M x16
  • 1.35V low voltage operation
• Micro USB connection
  • Full-speed (12Mbit) USB with direct connection to FPGA
• Non-volatile Storage
  • 128Mbit QSPI FLASH Memory
    • Bootloader (First 4Mbits)
    • User Bitstream
    • User storage (Firmware/MSC backend/etc)
    • QSPI compatible
  • MicroSD socket
    • 4bit SD interface (CK, CMD, DAT0-3)
• Power supply
  • High effeciency DCDC for main supplies
  • Battery charger (100mA), with charge indicator LED
  • LiPo battery connector (PH type)
• 48MHz onboard oscillator
• Standard 0.05" JTAG connector
• User I/O
  • 1x Button
  • 1x RGB LED
  • 20x I/O on 0.1" headers
• Analog System
  • Analog Mux
  • SAR ADC, external RC / input comparator of FPGA
  • Digital bypass
  • Internal channels for supply monitor
  • Battery voltage sensing
• Feather Format Board
  • Dimensions: 22.86mm x 50.8mm (0.9" x 2.0")

Pinouts #

DDR3 (IOVCC=1.35V) #

• Virtual VCCIO and GND are connected to VCCIO and GND on the PCB. They should be driven HIGH and LOW respectively to reduce SSO noise on the DDR3 I/O bank.

General (IOVCC=3.3V) #

Photos #